The present invention generally relates to the processing, such as the exposing, of a wafer edge, and more specifically relates to the use of a sensor to more precisely process the edge of wafer.
Getting the maximum usable area and highest yield from a wafer is critical to manufacturing integrated circuits cost effectively. Over the years, a number of methods have been developed to control the film stacks that occur on the wafer edge in order to reduce the defects that they cause. A common technique is to remove the resist build up, known as the edge bead, on the edge of the wafer with a combination of solvent dispense Edge Bead Remover (EBR) and Wafer Edge Expose (WEE). In recent years, additional techniques such as wet edge etching and edge scrub processes have been deployed as well.
While these processes remove or control films that are the source of defects, they do take up some space on the edge of the wafer. Initially, the industry standard for the non-yielding zone at the edge of the wafer, known as the “edge exclusion zone,” was 4 millimeters or more. As improved methods for controlling the films in this area became available, it has been possible to reduce this to about 3 millimeters or even 2 millimeters. The IRTS roadmap calls for reducing the edge exclusion zone to 1 millimeter by the year 2006.
The edge exclusion radius that must be used for determining wafer layouts and the number of yieldable die sites (also known as the gross die per wafer) is not actually the physical location of the edge film removals. In order for the die to be yielding at the 3 millimeter location, the physical edge settings must be closer to the edge than that since there are yield loss effects, typically due to CMP processes, that extend some distance from the film removal edge step. In addition, certain films must not be allowed to stack on top of each other or they will cause particle defects, so there must be room to put different layer edges in different locations within the edge zone.
FIG. 1 shows a typical plan for edge exposure settings used for a 3 millimeter edge exclusion strategy. In FIG. 1, reference numeral 10 identifies all BARC layers, reference numeral 12 identifies the darkfield WWE layers, reference numeral 14 identifies the brightfield WWE layers, and reference numeral 16 identifies the contact mask. It can be seen that the furthest inward physical edge (i.e., the edge 18 of the contact mask 16) is actually set at 1.9 millimeters.
Control of the edge removal settings with equipment available today is typically +/−0.2 millimeter. In order to guarantee no overlaps, each setting must be separated by at least 0.4 millimeter with an additional 0.4 millimeter allotted for the curvature at the edge of the wafer. With at least four non-overlapping settings needed (as shown in FIG. 2), this adds up to a minimum of at least 1.6 millimeters needed for physical edge settings.
The value of an extra yieldable millimeter at the edge of the wafer is considerable. For example, the difference between a 3 millimeter and a 2 millimeter edge setting can be worth an additional 10 to 30 die per wafer depending on die size. The increase in gross die per wafer represents a significant financial value for a typical wafer fabricator. Presently, at a run rate of 2000 wafers a week, the extra 12 die in the example above are worth an extra $58,000 per week (or $3,000,000 per year), for no additional processing cost.
In order to meet the IRTS roadmap of 1 millimeter edge exclusion, improvements in two key characteristics must occur:                1) Improve control of the edge film removal processes to +/−0.1 millimeter or less; and        2) Reduce the CMP edge yield effect to less than 0.2 millimeter.        
The subject of the present invention is to address the need to improve the edge film removal process to less than +/−0.1 millimeter, particularly the Wafer Edge Expose (WEE) used in photolithography and mask-less wafer edge etch processes, such as W and Low K wet etches, using spin processors.
The existing method for controlling edge removal settings such as the WEE is to use a mechanical set point on the WEE exposure unit and measure the results on the wafer. The edge exposure settings are adjusted on a set frequency and plotted in an SPC control chart. Improved systems utilize a programmable stepper motor to position the WEE unit, and these systems typically have an improved accuracy.
Currently in the industry, the WEE unit position is referenced to the resist coating unit itself and does not account for many key variations such as the placement of the wafer on the unit, variations in wafer diameter, and placement of previous WEE layers. FIG. 2 shows a top view of a wafer 20 and a Wafer Edge Expose unit 22, wherein the wafer is rotated (as represented by arrow 24) under the Wafer Edge Expose unit 22.
FIG. 3 provides a cross sectional view of the wafer 20 and Wafer Edge Expose unit 22. Specifically, reference numeral 26 identifies the vacuum chuck which holds the wafer 20, reference numeral 28 identifies the resist which is on the wafer 20, reference numeral 30 identifies the resist edge bead, reference numeral 32 identifies UV light which is produced by the edge expose unit 22, and reference numeral 34 identifies the wafer edge expose drive motor and controller. FIG. 3 also illustrates the many different tolerances or variations which can add up to an unacceptable WEE placement error. Specifically, reference numeral 36 identifies the wafer centering tolerance, reference numeral 38 identifies the wafer edge expose unit tolerance (i.e., with regard to placement relative to a centerline 39 of the chuck), and reference numeral 40 identifies the wafer diameter tolerance.